The Bank Nth Chance Replacement Policy for FPGA-Based CAMs

Author:

Berube Paul,Zinyk Ashley,Amaral José Nelson,MacGregor Mike

Publisher

Springer Berlin Heidelberg

Reference17 articles.

1. Brelet, J.-L., New, B.: Designing Flexible, Fast CAMs with Virtex Family FPGAs, Xilinx, version 1.1 edn. (September 1999), http://www.xilinx.com/xapp/xapp203.pdf

2. Chivin, L., Duckworth, R.: Content-addressable and associative memory: Alternatives to the ubiquitous ram. IEEE Computer Magazine 22(7), 51–64 (1989)

3. Chvets, I.: Multi-zone caching for ip address lookup. Master’s thesis, University of Alberta, Edmonton, AB, Computing Science (2002)

4. Chiueh, T.C., Pradhan, P.: High performance IP routing table lookup using CPU caching. IEEE INFOCOMM (3), 1421–1428 (1999)

5. Ditmar, J.M.: A dynamically reconfigurable fpga-based content addressable memory for ip characterization. Master’s thesis, Royal Institute of Technology, Stockholm (2000)

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3. FPGA implementation and experimental evaluation of a multizone network cache;Microprocessors and Microsystems;2004-08

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