1. M.J. Akhbarizadeh, M. Nourani, Efficient prefix cache for network processors, in: 12th Annual IEEE Symposium on High Performance Interconnects, August 2004, pp. 41–46.
2. Throughput increase in packet forwarding engines using adaptive block-selection scheme;Akhbarizadeh;IEEE Communications Letters,2005
3. FPGA implementation experimental evaluation of a prototype multizone network cache;Berube;Microprocessors and Microsystems,2004
4. P. Berube, A. Zinyk, J.N. Amaral, M. MacGregor, The bank Nth chance replacement policy for FPGA-based CAMs, in: International Conference on Field Programmable Logic and Applications (FPL), Lisbon, Portugal, September 2003, pp. 648–660.
5. L. Bhuyan, H. Wang, Execution-driven simulation of IP router architectures, in: International Symposium on Network Computing and Applications, October 2001, pp. 145–155.