Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-013-5404-x.pdf
Reference34 articles.
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2. Chakravadhanula K (2009) Capture power reduction using clock gating aware test generation. Proc Intl Test Conf:1–9
3. Chou R, Saluja K, Agrawal V (1997) Scheduling tests for VLSI systems under power constraints. IEEE Trans VLSI Syst 5(6):175–185
4. Czysz D, Kassab M, Lin X, Mrugalski G, Rajski J, Tyszer J (2008) Low power scan shift and capture in the EDT environment. Proc Intl Test Conf:1–10
5. Dabholkar V, Chakravarty S, Pomeranz I, Reddy S (1998) Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans Comput-Aided Des 17:1325–1333
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test;2016 IEEE 25th Asian Test Symposium (ATS);2016-11
2. Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets;Journal of Electronic Testing;2014-09-06
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