Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-014-5472-6.pdf
Reference39 articles.
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3. Corno F, Prinetto P, Rebaudengo M, Sonza-Reorda M (1998) A test pattern generation methodology for low power consumption. In: VLSI test symposium, pp 453–457
4. Czutro A, Sauer M, Polian I, Becker B (2012) Multi-conditional SAT-ATPG for power-droop testing. In: IEEE European test symposium, pp 1–6
5. Drechsler R, Eggersglüß S, Fey G, Glowatz A, Hapke F, Schloeffel J, Tille D (2008) On acceleration of SAT-based ATPG for industrial designs. IEEE Trans Comput-Aided Des Integ Circuits Syst 27(7):1329–1333
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