Minimizing peak current in combinational circuit test
Author:
Publisher
Journal of Engineering Research
Subject
General Engineering
Reference29 articles.
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2. Borowczak, M. & Vemuri, R. 2014. Enabling side channel secure FSMs in the presence of low power requirements. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI. pp. 232-235.
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4. Chattopadhyay, S. & Choudhary, N. 2003. Genetic algorithm based approach for low power combinational circuit testing. In Proceedings of the 16th IEEE International Conference on VLSI Design. pp. 552-557.
5. Dutta, A., Kundu, S. & Chattopadhyay, S. 2013. Thermal aware don’t care filling to reduce peak temperature and thermal variance during testing. In Proceedings of the 22nd Asian Test Symposium. pp. 25-30.
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1. Paul and the old testament;Studia Theologica - Nordic Journal of Theology;1971-01
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