A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy

Author:

Chang Da-Ming,Li Jin-Fu,Huang Yu-Jen

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Reference20 articles.

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3. Huang R-F, Li J-F, Yeh J-C, Wu C-W (2002) A simulator for evaluating redundancy analysis algorithms of repairable embedded memories. In: Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT). Isle of Bendor, France, pp 68–73, July

4. Huang W-K, Shen Y-N, Lombardi F (1990) New approaches for the repair of memories with redundancy by row/column deletion for yield enhancement. IEEE Trans Comput-Aided Des Integr Circuits Syst 9(3):323–328, Mar

5. Kawagoe T, Ohtani J, Niiro M, Ooishi T, Hamada M, Hidaka H (2000) A built-in self-repair analyzer (CRESTA) for embedded DRAMs. In: Proc. Int’l Test Conf. (ITC), pp 567–574

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