Memory test and repair technique for SoC based devices-Reference-Cited by-同舟云学术

Memory test and repair technique for SoC based devices

Published:2021-04-25 Issue:8 Volume:18 Page:20210092-20210092
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Ahmed Mohammed Altaf¹,Eljialy Abubaker E.M.²,Ahmad Sultan³

Affiliation:

1. Department of Computer Engineering, College of Computer Engineering and Sciences, Prince Sattam bin Abdulaziz University

2. Department of Information System, College of Computer Engineering and Sciences, Prince Sattam bin Abdulaziz University

3. Department of Computer Science, College of Computer Engineering and Sciences, Prince Sattam bin Abdulaziz University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/18/8/18_18.20210092/_pdf

Reference31 articles.

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2. [2] A. Bosio, et al.: Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies (Springer-Verlag US, 2009) (DOI: 10.1007/978-1-4419-0938-1).

3. [3] D.-M. Chang, et al.: “A built-in redundancy-analysis scheme for random access memories with two-level redundancy,” J. Electron. Test 24 (2008) 181 (DOI: 10.1007/s10836-007-5032-4).

4. [4] M.A. Ahmed, et al.: “FPGA based high speed memory BIST controller for embedded applications,” IJST 8 (2015) 1 (DOI: 10.17485/ijst/2015/v8i33/76080).

5. [5] O. Hasan, et al.: “Formal probabilistic analysis of stuck-at fault in reconfigurable memory array,” 7th Int. Conf. IFM (2009) 277 (DOI: 10.1007/978-3-642-00255-7_19).

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3. Generation of New Low-Complexity March Algorithms for Optimum Faults Detection in SRAM;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022

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