A built-in self-repair analyzer (CRESTA) for embedded DRAMs

Author:

Kawagoe T.,Ohtani J.,Niiro M.,Ooishi T.,Hamada M.,Hidaka H.

Publisher

Int. Test Conference

Cited by 96 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. GRAP: Efficient GPU-Based Redundancy Analysis Using Parallel Evaluation for Cross Faults;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08

2. Bridging Repairability Gaps in Shared Bus Architecture with Shared Physical Memory Implementation;2023 IEEE International Test Conference India (ITC India);2023-07-23

3. RA-Aware Fail Data Collection Architecture for Cost Reduction;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023

4. A New Fail Address Memory Architecture for Cost-Effective ATE;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023

5. Efficient Repair Analysis Algorithm Exploration for Memory With Redundancy and In-Memory ECC;IEEE Transactions on Computers;2021-05-01

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