Author:
SenGupta Breeta,Ingelsson Urban,Larsson Erik
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Reference19 articles.
1. Chou RM, Saluja KK, Agrawal VD (1997) Scheduling tests for VLSI systems under power constraints. IEEE Trans Very Large Scale Integr (VLSI) Syst 5(2):175–185
2. Hopper E, Turton BCH (2001) An empirical investigation of meta-heuristic and heuristic algorithms for a 2D packing problem. Eur J Oper Res 128:34–57
3. Iyengar V, Chakrabarty K, Marinissen EJ (2002) Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs, no 44.3, pp 685–690
4. Iyengar V, Chakrabarty K, Marinissen EJ (2002) Test wrapper and test access mechanism co-optimization for system-on-chip. J Electron Test: Theory Appl 18:213–230
5. Iyengar V, Chakrabarty K, Marinissen EJ (2003) Test access mechanism optimization, test scheduling, and tester data volume reduction for system-on-chip. IEEE Trans Comput 52(12):1619–1632
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