Test Flow Selection for Stacked Integrated Circuits
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-019-05813-z.pdf
Reference15 articles.
1. Agrawal M, Chakrabarty K (2015) Test-Cost Modeling and Optimal Test-Flow Selection of 3-D-Stacked ICs. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 1523–1536
2. Chou RM, Saluja KK, Agrawal VD (1997) Scheduling tests for VLSI systems under power constraints. IEEE Trans VLSI Syst 5(2):175–185
3. Hamdioui S, Taouil M (2011) Yield Improvement and Test Cost Optimization for 3D Stacked ICs. In: Asian Test Symposium (ATS), pp 480–485
4. Higgins M, MacNamee C, Mullane B (2010) Design and implementation challenges for adoption of the IEEE 1500 standard. IET Comput Digit Techn 4(1):38–49
5. Iyengar V, Chakrabarty K, Marinissen EJ (2002) Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip. In: Journal of Electronic Testing: Theory and Applications, vol 18, pp 213–230
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