A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs

Author:

Agrawal Mukesh,Chakrabarty Krishnendu,Eklow Bill

Funder

Semiconductor Research Corporation

Cisco Systems through the Silicon Valley Community Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. On Managing Test-Time, Power, and Layer Assignment in 3D SoCs with Built-In-Self-Repair Modules;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

2. Built in Self Test on Random Test Pattern Generation for Test Compression;2023 International Conference on Self Sustainable Artificial Intelligence Systems (ICSSAS);2023-10-18

3. Design of TPG BIST Using Various LFSR for Low Power and Low Area;Communication, Software and Networks;2022-10-28

4. Storage-Based Logic Built-In Self-Test with Variable-Length Test Data;2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2022-10-19

5. 3D IC Memory BIST Controller Allocation for Test Time Minimization Under Power Constraints;2017 IEEE 26th Asian Test Symposium (ATS);2017-11

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