Design of TPG BIST Using Various LFSR for Low Power and Low Area

Author:

Bhandari Jugal Kishore,Verma Yogesh Kumar

Publisher

Springer Nature Singapore

Reference10 articles.

1. Bushgnell ML, Agrawal VD (2004) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits

2. Zorian Y (1993) A distributed BIST control scheme for complex VLSI devices. In: Proceeding VLSI test symposium, pp 4–9

3. Girard P (2002) Survey of low-power testing of VLSI circuits. IEEE Des Test Comput 19(3):80–90

4. Girard P, Guiller L, Landrault C, Pravossoudovitch S, Wunderlich HJ (2001) A modified clock scheme for a low power BIST test pattern generator. In: 19th IEEE Proceeding VLSI test symposium, CA, pp 306–311

5. Design of Low Power TPG BIST Technique using LP-LFSR, Kavitha A, Seetharaman G, Prabakar TN, Shrinithi S (2013) A 2013 third international conference in intelligent systems modelling and simulation

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