Built in Self Test on Random Test Pattern Generation for Test Compression-Reference-Cited by-同舟云学术

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Built in Self Test on Random Test Pattern Generation for Test Compression

Published:2023-10-18 Issue: Volume: Page:
ISSN:
Container-title:2023 International Conference on Self Sustainable Artificial Intelligence Systems (ICSSAS)
language:
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Author:

Ravi R.¹,Kannadhasan S.²,Ramachandran K.³,Deepa K.⁴,Thabathi R.⁴,Kalaivani S.⁴

Affiliation:

1. Francis Xavier Engineering College,Dept of CSE,Tirunelveli,India

2. Study World College of Engineering,Dept of ECE,Coimbatore,India

3. Study World College of Engineering,Dept of Mechanical,Coimbatore,India

4. Study World College of Engineering,Dept of CSE,Coimbatore,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10330805/10331621/10331724.pdf?arnumber=10331724

Reference8 articles.

1. Challenges and Future Perspectives of Low-Power VLSI Circuits: A Study

2. Testability Evaluation for Local Design Modifications

3. Dual-Gate Organic Thin-Film Transistor and Multiplexer Chips for the Next Generation of Flexible EG-ISFET Sensor Chips

4. VLSI test through an improved LDA classification algorithm for test cost reduction

5. A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs

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