On Chip Signal Generators for Low Overhead ADC BIST
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering
Link
http://link.springer.com/content/pdf/10.1007/s10836-012-5320-5.pdf
Reference13 articles.
1. Azaïs F, Bernard S, Bertrand Y, Renovell M (2001) A low-cost BIST architecture for linear histogram testing of ADCs. J Electron Test Theory Appl 17:139–147
2. Bult K (2009) “Embedded analog-to-digital converters”. Proc. IEEE ESSCIRC’09, Sep, pp 52–64
3. Chen H, Wang C, Su C (2002) “A self calibrated ADC BIST methodology”. IEEE VLSI Test Symposium, pp 117–122
4. Flores M, Negreiros M et al (2005) Low cost BIST for static and dynamic testing of ADCs. J Electron Test Theory Appl 21:283–290
5. Huang JH, Liu ZH, Jeng MC, Ko PK, Hu C (1992) “A physical model for MOSFET output resistance”. In: IEDM Tech. Dig. pp 569–572
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