Power-Aware System-Level Test Planning-Reference-Cited by-同舟云学术

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Power-Aware System-Level Test Planning

Published:2009-08-13 Issue: Volume: Page:175-211
ISSN:
Container-title:Power-Aware Testing and Test Strategies for Low Power Devices
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Author:

Larsson Erik,Ravikumar C. P.

Publisher

Springer US

Link

http://link.springer.com/content/pdf/10.1007/978-1-4419-0928-2_6.pdf

Reference83 articles.

1. Abadir MS, Breuer MA (1986) Test schedules for VLSI circuits having built-in test hardware. IEEE Trans Comput 35(4):361–367. DOI http://dx.doi.org/10.1109/TC.1986.1676771

2. Aerts J, Marinissen EJ (1998) Scan chain design for test time reduction in core-based ICs. In: Proceedings of IEEE international test conference (ITC), pp 448–457

3. Beenker FPM, Eerdewijk KJE, Gerritsen RBW, Peacock FN, Star MD (1986) Macro testing: unifying ic and board test. IEEE Design Test Comput 3(6):26–32. DOI http://dx.doi.org/ 10.1109/MDT.1986.295048

4. Bhatia S, Gheewala T, Varma P (1996) A unifying methodology for intellectual property and custom logic testing. In: Proceedings of IEEE international test conference (ITC), pp 639–648

5. Bonhomme Y, Girard P, Guiller L, Landrault C, Pravossoudovitch S (2001) A gated clock scheme for low power scan testing of logic ICs or embedded cores. In: Proceedings of IEEE Asian test symposium (ATS), pp 253–258

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