Author:
Bhatia S.,Gheewala T.,Varma P.
Cited by
19 articles.
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1. Power-Aware System-Level Test Planning;Power-Aware Testing and Test Strategies for Low Power Devices;2009-08-13
2. Isolation Techniques for Soft Cores;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2008-08
3. Low-power multi-core ATPG to target concurrency;Integration;2008-07
4. InTeRail: a test architecture for core-based SOCs;IEEE Transactions on Computers;2006-02
5. Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability;14th Asian Test Symposium (ATS'05);2005