Author:
Beenker F.P.M.,Eerdewijk K.j.e. Van,Gerritsen R.B.W.,Peacock F.N.,Der Star M. Van
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software,Electrical and Electronic Engineering,Hardware and Architecture,Software
Cited by
24 articles.
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1. Power-Aware System-Level Test Planning;Power-Aware Testing and Test Strategies for Low Power Devices;2009-08-13
2. InTeRail: a test architecture for core-based SOCs;IEEE Transactions on Computers;2006-02
3. Resource-constrained system-on-a-chip test: a survey;IEE Proceedings - Computers and Digital Techniques;2005
4. Advanced topics of DFT technologies in a general purposed CPU chip;2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03;2003
5. The role of test protocols in automated test generation for embedded-core-based system ICs;Journal of Electronic Testing;2002