Device Physics and Performance Potential of III-V Field-Effect Transistors
Author:
Publisher
Springer US
Link
http://link.springer.com/content/pdf/10.1007/978-1-4419-1547-4_3.pdf
Reference48 articles.
1. D. A. Antoniadis and A. Khakifirooz, “MOSFET performance scaling: Limitations and future options,” IEEE International Electron Devices Meeting 2008, Technical Digest, pp. 253–256, 2008.
2. K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C. H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hatttendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pei, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Schifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, “A 45 nm logic technology with high-k plus metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging,” 2007 IEEE International Electron Devices Meeting, vol. 1 and 2, pp. 247–250, 2007.
3. S. Natarajan, M. Armstrong, M. Bost, R. Brain, M. Brazier, C.-H. Chang, V. Chikarmane, and M. Childs, “A 32 nm logic technology featuring 2nd-generation High-k+Metal-Gate transistors, enhanced channel strain and 0.171 um2 SRAM cell size in a 291 Mb array,” 2008 IEEE International Electron Devices Meeting, pp. 941–943, 2008.
4. M. Passlack, P. Zurcher, K. Rajagopalan, R. Droopad, J. Abrokwah, M. Tutt, Y. B. Park, E. Johnson, O. Hartin, A. Zlotnicka, P. Fejes, R. J. W. Hill, D. A. J. Moran, X. Li, H. Zhou, D. Macintyre, S. Thoms, A. Asenov, K. Kalna, and I. G. Thayne, “High mobility III-V MOSFETs for RF and digital applications,” 2007 IEEE International Electron Devices Meeting, vol. 1 and 2, pp. 621–624, 2007.
5. Y. Sun, E. W. Kiewra, J. P. de Souza, J. J. Bucchignano, and K. E. Fogel, “Scaling of In_{0.7}Ga_{0.3}As buried-channel MOSFETs,” 2008 IEEE International Electron Devices Meeting, pp. 367–370, 2008.
Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Complete Analytical RF Model for Nanoscale Semiconductor-On-Insulator MOSFET;Silicon;2022-11-28
2. Impact of InGaAs Thickness and Indium Content on the Performance of (InP/InGaAs/InAlAs) MOSFET Structure;Lecture Notes in Electrical Engineering;2020-08-15
3. Investigation of the UTB-InAs-MOSFETs structure;Materials Science in Semiconductor Processing;2019-06
4. III-V Devices and Technology for CMOS;High Mobility Materials for CMOS Applications;2018
5. Unequivocal determination of complex molecular structures using anisotropic NMR measurements;Science;2017-04-07
1.学者识别学者识别
2.学术分析学术分析
3.人才评估人才评估
"同舟云学术"是以全球学者为主线，采集、加工和组织学术论文而形成的新型学术文献查询和分析系统，可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容，当前同舟云学术共收录了国内外主流学术期刊6万余种，收集的期刊论文及会议论文总量共计约1.5亿篇，并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询！咨询电话：010-8811{复制后删除}0370
www.globalauthorid.com
TOP
Copyright © 2019-2024 北京同舟云网络信息技术有限公司 京公网安备11010802033243号 京ICP备18003416号-3