MOSFET performance scaling: Limitations and future options
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/4786613/4796592/04796665.pdf?arnumber=4796665
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1. Analysis of Source-and-Drain Doping for the Underlapped FinFET;2024 IEEE International Conference on Omni-layer Intelligent Systems (COINS);2024-07-29
2. Implementation and performance analysis of QPSK system using pocket double gate asymmetric JLTFET for satellite communications;Scientific Reports;2023-02-21
3. Negative-Bias-Stress and Total-Ionizing-Dose Effects in Deeply Scaled Ge-GAA Nanowire pFETs;IEEE Transactions on Nuclear Science;2022-03
4. Formation and characterization of Ni, Pt, and Ti stanogermanide contacts on Ge0.92Sn0.08;Thin Solid Films;2019-11
5. Layout Study of Strained Ge-Based pMOSFETs Integrated With S/D GeSn Alloy and CESL by Using Process-Oriented Stress Simulations;IEEE Transactions on Electron Devices;2018-11
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