1. Design of ion-implanted MOSFETs with very small physical dimensions;Dennard;IEEE J. Solid-State Circuits,1974
2. Uniaxial-process-induced strained-Si: extending the CMOS roadmap;Thompson;IEEE Trans. Electron Devices,2006
3. A 45nm logic technology with high-k plus metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging;Mistry,2007
4. A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications;Jan,2012
5. Dark silicon and the end of multicore scaling;Esmaeilzadeh,2011