Warpage Characterization of Molded Wafer for Fan-Out Wafer-Level Packaging
Author:
Affiliation:
1. Department of Aerospace and Systems Engineering, Feng Chia University, Taichung, Taiwan 407, China
2. Program of Mechanical and Aeronautical Engineering, Feng Chia University, Taichung, Taiwan 407, China
Abstract
Funder
Ministry of Science and Technology, Taiwan, ROC
Publisher
ASME International
Subject
Electrical and Electronic Engineering,Computer Science Applications,Mechanics of Materials,Electronic, Optical and Magnetic Materials
Link
http://asmedigitalcollection.asme.org/electronicpackaging/article-pdf/doi/10.1115/1.4044625/5227335/ep-19-1023.pdf
Reference20 articles.
1. Design and Reliability Assessment of Novel 3D-IC Packaging;J. Mech.,2017
2. Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging;ASME J. Electron. Packag.,2019
3. An Embedded Device Technology Based on a Molded Reconfigured Wafer,2006
4. The Redistributed Chip Package: A Breakthrough for Advanced Packaging,2007
5. InFO (Wafer Level Integrated Fan-Out) Technology,2016
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