Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack

Abstract

A numerical assessment on the thermal stress in a three-dimensional (3D) microelectronic package structure is performed. The objectives are to study how the chip stack/microbump assembly responds to thermal mismatch induced deformation, and its influences on the electrical performance of devices. The 3D finite element model features a copper through-silicon-via (TSV)/microbump bonding structure connecting two adjacent silicon chips, with and without an underfill layer in between. A case that the entire solder layer has been transformed into an intermetallic layer is also considered. Potential for damage initiation is examined by the measure of stress and strain patterns. It was found that the part of TSV well inside the silicon chip is under high triaxial tensile stresses after thermal cooling, and plastic deformation in copper occurs in and around the microbump regions. The existence of underfill increases plastic strains in the solder joint. The underfill also leads to a significant change in local stress field when the soft solder is transformed entirely into an intermetallic layer. The carrier mobility for the p- and n-type devices is influenced by the stresses in silicon near the TSV; the sizes of “keep-out zone” for the various model configurations are also quantified.