An anisotropic thermal-stress model for through-silicon via
Author:
Publisher
IOP Publishing
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
http://stacks.iop.org/1674-4926/39/i=2/a=026003/pdf
Reference17 articles.
1. The chips are down for Moore’s law
2. Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV)
3. Analysis of Thermal Stress and Its Influence on Carrier Mobility in Three-Dimensional Microelectronic Chip Stack
4. Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects
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