UV Laser Releasable Temporary Bonding Materials for FO-WLP
Author:
Affiliation:
1. Advanced Electronic Materials Laboratory, Fine Electronic Materials Research Laboratories
Publisher
Japan Institute of Electronics Packaging
Link
https://www.jstage.jst.go.jp/article/jiepeng/11/0/11_E18-004-1/_pdf
Reference14 articles.
1. [1] G. J. Jung, "Structure and Process Development of Wafer Level Embedded SiP (System in package) for Mobile Applications," 2009 11th EPTC, p. 191.
2. [2] Y. Kurita, "A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology," 2007 ECTC, p. 821.
3. [3] S. Yoon, et al., "Mechanical Characterization of Next Generation eWLB (embedded Wafer Level BGA) Packaging," ECTC, pp. 441–446, 2011.
4. [4] M. Santarini, "Stacked and Loaded: Xilinx SSI, 28-Gbps I/O Yield Amazing FPGAs," Xcell Journal, No. 74, pp. 8–13, 2011.
5. [5] M. Murugesan, et al., "Wafer Thinning, Bonding, and Interconnects Induced Local Strain/Stress in 3D-LSIs with Fine-Pitch High-Density Microbumps and Through-Si Vias," IEDM, pp. 2.3.1-2.3.4, December 2010.
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