Wettability and Reliability for Double-Sided Assembly with Chip Connection (C2) Flip-Chip Technology

Author:

Noma Hirokazu,Oyama Yukifumi,Nishiwaki Hidetoshi,Takami Masahide,Takatani Toshiyuki,Toriyama Kazushige,Orii Yasumitsu

Publisher

Japan Institute of Electronics Packaging

Reference6 articles.

1. [1] W. Koh, "System in package (SiP) technology applications", International Conference on Electronic Packaging Technology, pp. 61–66, August 2005.

2. [2] C. Ryu et al., "Novel Approaches to Current BGA Packaging Challenges", Electronics Packaging Technology Conference, pp. 1258–1263, December 2008.

3. [3] Y. Orii et al., "Ultrafine-Pitch C2 Flip Chip Interconnections with Solder-Capped Cu Pillar Bumps", Electronic Components and Technology Conference, pp. 948–953, May 2009.

4. [4] D. Kin et al., "Evaluation of DIG (Direct Immersion Gold) as a New Surface Finish for Mobile Applications", Electronic Components and Technology Conference, pp. 258–262, June 2006.

5. [5] J. Lee, "The Sn Whisker Growth Evolution of IC Packaging on the PC Board Assembly", Electronic Components and Technology Conference, pp. 1964–1970, May 2007.

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