Device Reliability to Circuit Qualification: Insights and Challenges
Author:
Affiliation:
1. ST Microelectronics,Crolles,France,38926
2. ISEN Yncréa Méditerranée, IM2NP UMR 7334,Maison des Technologies,Toulon,France,83000
3. ST Microelectronics,Greater Noida,Uttar Pradesh,India,20130
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10032732/10032733/10077885.pdf?arnumber=10077885
Reference32 articles.
1. Experimental Proof of the Drain-Side Dielectric Breakdown of HKMG nMOSFETs Under Logic Circuit Operation
2. Modeling hot carrier damage interaction between on and off modes for 28 nm AC RF applications
3. Hot-Carrier acceleration factors for low power management in DC-AC stressed 40nm NMOS node at high temperature
4. Hot-Carrier degradation in P- and N-channel EDMOS for smart power application
5. New Modelling Off-state TDDB for 130nm to 28nm CMOS nodes
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1. Universal Dielectric Breakdown Modeling Under Off-State TDDB for Ultra-Scaled Device From 130nm to 28nm Nodes and Beyond;IEEE Transactions on Device and Materials Reliability;2024-06
2. Location of Oxide Breakdown Events under Off-state TDDB in 28nm N-MOSFETs dedicated to RF applications;2023 IEEE International Reliability Physics Symposium (IRPS);2023-03
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