Failure Analysis of 65nm CMOS Integrated Nanoscale ReRAM Devices on a 300mm Wafer Platform
Author:
Affiliation:
1. SUNY Polytechnic Institute,College of Nanoscale Science and Engineering,Albany,NY,USA,12203
Funder
Air Force Research Laboratory
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10032732/10032733/10032747.pdf?arnumber=10032747
Reference26 articles.
1. Impact of Etch Process on Hafnium Dioxide Based Nanoscale RRAM Devices
2. Nanoscale Hafnium Oxide RRAM Devices Exhibit Pulse Dependent Behavior and Multi-level Resistance Capability
3. Voltage-Controlled Cycling Endurance of HfOx-Based Resistive-Switching Memory
4. Metal-oxide resistive random access memory (RRAM) technology: Material and operation details and ramifications
5. Optimization of Switching Metrics for CMOS Integrated HfO2 based RRAM Devices on 300 mm Wafer Platform
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