A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface-Reference-Cited by-同舟云学术

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A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface

Published:2014-04 Issue:4 Volume:49 Page:1048-1062
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Hossain Masum,Aquil Farrukh,Chau Pak Shing,Tsang Brian,Le Phuong,Wei Jason,Stone Teva,Daly Barry,Tran Chanh,Eble John C.,Knorpp Kurt,Zerbe Jared L.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6777594/06731609.pdf?arnumber=6731609

Cited by 18 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A shared TDC-based fast-lock all-digital DLL using a DCC-embedded delay line;Microelectronics Journal;2024-07

2. A Shared Tdc-Based Fast-Lock All-Digital Dll Using a Dcc-Embedded Delay Line;2024

3. A Small Area Cyclic Vernier Delay Line TDC Based ADDLL using Linear Delay Inverter;2023 20th International SoC Design Conference (ISOCC);2023-10-25

4. Dual Sawtooth-Based Delay Locked Loops for Heterogeneous 3-D Clock Networks;2023 IEEE 36th International System-on-Chip Conference (SOCC);2023-09-05

5. A Wide-Range All-Digital Delay-Locked Loop for DDR1–DDR5 Applications;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-10

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