Dual Sawtooth-Based Delay Locked Loops for Heterogeneous 3-D Clock Networks

Author:

Ayes Andres1,Friedman Eby G.1

Affiliation:

1. University of Rochester,Department of Electrical and Computer Engineering,Rochester,New York

Funder

National Science Foundation

Publisher

IEEE

Reference17 articles.

1. All-digital delay-locked loop for 3D-IC die-to-die clock synchronization

2. A Multiphase DLL with a Novel Fast-Locking Fine-Code Time-to-Digital Converter;zhang;IEEE Trans Very Large Scale Integ (VLSI) Syst,2014

3. An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line

4. Design of a digital IP for 3D-IC die-to-die clock synchronization

5. A 1.74 mW/GHz 0.11–2.5 GHz Fast-Locking, Jitter-Reducing, 180 Phase-Shift Digital DLL with a Window Phase Detector for LPDDR4 Memory Controllers;chae;Proceedings of the IEEE Asian SolidState Circuits Conference,2015

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