A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC-Reference-Cited by-同舟云学术

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A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC

Published:2015-02 Issue:2 Volume:50 Page:543-555
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Hong Hyeok-Ki,Kim Wan,Kang Hyun-Wook,Park Sun-Jae,Choi Michael,Park Ho-Jin,Ryu Seung-Tak

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/7024661/06967867.pdf?arnumber=6967867

Cited by 74 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications;Engineering Research Express;2024-02-15

3. A 0.55-mm2 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture;Microelectronics Journal;2024-02

4. A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta–Sigma Modulator With Digital Noise Coupling;IEEE Journal of Solid-State Circuits;2024

5. LMS-Based Background Calibration of Bit Weights in SAR ADC Using Reinforcement Learning Optimization;Circuits, Systems, and Signal Processing;2023-11-15

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