A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS-Reference-Cited by-同舟云学术

A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS

Published:2019-12 Issue:12 Volume:54 Page:3478-3492
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Liu Hanli^ORCID,Shirane Atsushi,Okada Kenichi^ORCID,Sun Zheng,Huang Hongye^ORCID,Deng Wei^ORCID,Siriburanon Teerachot^ORCID,Pang Jian^ORCID,Wang Yun^ORCID,Wu Rui^ORCID,Someya Teruki^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/8910478/08834854.pdf?arnumber=8834854

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