A Fractional-N DTC-based ADPLL using path-select multi-delay line TDC and true fractional division technique
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
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1. A DPLL-centric bluetooth low-energy transceiver with a 2.3-mW interference-tolerant hybrid-loop receiver in 65-nm CMOS;Liu;IEEE J. Solid State Circ.,2018
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3. A 2.9–4.0-GHz fractional-N digital PLL with bang-bang phase detector and 560-fs rms integrated jitter at 4.5-mW power;Tasca;IEEE J. Solid State Circ.,2011
4. A 265-μW fractional-N digital PLL with seamless automatic switching sub-sampling/sampling feedback path and duty-cycled frequency-locked loop in 65-nm CMOS;Liu;IEEE J. Solid State Circ.,2019
5. A 3.7 mW low-noise wide-bandwidth 4.5 GHz digital fractional-N PLL using time amplifier-based TDC;Elkholy;IEEE J. Solid State Circ.,2015
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