A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS-Reference-Cited by-同舟云学术

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A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS

Published:2020-08 Issue:8 Volume:55 Page:2285-2294
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Hong Cheng-Yao^ORCID,Liu Tsung-Te^ORCID

Funder

Ministry of Science and Technology, Taiwan

Intelligent and Sustainable Medical Electronics Research Fund in National Taiwan University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9146394/08906049.pdf?arnumber=8906049

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. iEDCL: Streamlined, False-Error-Free Error Detection and Correction Scheme in a Near-Threshold Enabled 32-bit Processor;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08

2. Margin Elimination in a 55 nm Near-Threshold Microcontroller with Adaptive Prediction Capability and Voltage Scaling;Electronics;2024-03-26

3. An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC–DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2023-11

4. A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-10

5. Automated In-Situ Monitoring for Variability-Resilient and Energy-Efficient Digital Circuits Demonstrated on a Viterbi Decoder in 22-nm CMOS;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-09

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