A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router-Reference-Cited by-同舟云学术

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A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router

Published:2023-10 Issue:10 Volume:70 Page:3787-3791
ISSN:1549-7747
Container-title:IEEE Transactions on Circuits and Systems II: Express Briefs
language:
Short-container-title:IEEE Trans. Circuits Syst. II

Author:

Pei Bingxi¹^ORCID,Xu Shi²,Luo Zhang³,Wang Qin¹^ORCID,Lai Mingche¹,He Weifeng¹^ORCID

Affiliation:

1. Department of Micro-Nano Electronics of SEIEE, Shanghai Jiao Tong University, Shanghai, China

2. Artificial Intelligence Research Center, National Innovation Institute of Defense Technology, Beijing, China

3. College of Computer, National University of Defense Technology, Changsha, China

Funder

National Key Research and Development Program of China

NSFC

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8920/10262390/10160105.pdf?arnumber=10160105

Reference21 articles.

1. Near- and Sub- $V_{t}$ Pipelines Based on Wide-Pulsed-Latch Design Techniques

2. R-processor: 0.4V resilient processor with a voltage-scalable and low-overhead in-situ error detection and correction technique in 65nm CMOS

3. A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking

4. TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS

5. Sharp - A Resilient Asynchronous Template

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