Automated In-Situ Monitoring for Variability-Resilient and Energy-Efficient Digital Circuits Demonstrated on a Viterbi Decoder in 22-nm CMOS-Reference-Cited by-同舟云学术

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Automated In-Situ Monitoring for Variability-Resilient and Energy-Efficient Digital Circuits Demonstrated on a Viterbi Decoder in 22-nm CMOS

Published:2023-09 Issue:9 Volume:31 Page:1320-1329
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Nieto Taladriz Clara¹^ORCID,Dehaene Wim¹^ORCID

Affiliation:

1. Department of Electrical Engineering (ESAT), Katholieke Universiteit Leuven (KU Leuven), Leuven, Belgium

Funder

KULeuven Methusalem Project INPACT

Flanders AI Project IMPULS

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/10229811/10163757.pdf?arnumber=10163757

Reference25 articles.

1. TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS

2. Margin Elimination Through Timing Error Detection in a Near-Threshold Enabled 32-bit Microcontroller in 40-nm CMOS

3. A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS

4. A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS

5. iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor

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