Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Cited by
21 articles.
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1. An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-07
2. Design of a 10-BIT 100MSPS Sar ADC;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17
3. A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation;IEEE Transactions on Circuits and Systems I: Regular Papers;2022-10
4. A SAR ADC with Reconfigurable Delay and Redundancy to Relax the Reference Driver;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28
5. A 2.1 mW 2 MHz-BW 73.8 dB-SNDR Buffer-Embedded Noise-Shaping SAR ADC;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-12