An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend-Reference-Cited by-同舟云学术

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An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend

Published:2024-07 Issue:7 Volume:32 Page:1195-1204
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Huang Siji¹^ORCID,Basak Debajit²,Chen Yanhang¹^ORCID,Huang Qifeng¹^ORCID,Fan Yifei¹^ORCID,Yuan Jie¹^ORCID

Affiliation:

1. Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kong, China

2. Atom Semiconductor, Hong Kong, China

Funder

Hong Kong Government Innovation and Technology Commission

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/92/10576042/10510262.pdf?arnumber=10510262

Reference40 articles.

1. A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR- $\Delta \Sigma $ ADC With On-Chip Buffer in 28 nm CMOS

2. A 0.47–1.6 mW 5-bit 0.5–1 GS/s Time-Interleaved SAR ADC for Low-Power UWB Radios

3. Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver

4. A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 $\times$ 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC

5. A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique

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