A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation

Author:

Shen Yi1ORCID,Tang Xiyuan2,Xin Xin3,Liu Shubin4ORCID,Zhu Zhangming1ORCID,Sun Nan5

Affiliation:

1. Hangzhou Institute of Technology, Xidian University, Hangzhou, China

2. Department of Micro/Nanoelectronics, Institute for Artificial Intelligence, Peking University, Beijing, China

3. School of Electronic Engineering, Xi’an University of Posts and Telecommunications, Xi’an, China

4. School of Microelectronics, Xidian University, Xi’an, China

5. Department of Electronic Engineering, Tsinghua University, Beijing, China

Funder

National Natural Science Foundation of China

Zhejiang Provincial Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Enhancing Performance of SAR ADC through Supervised Machine Learning;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Machine Learning Based Static and Dynamic Error Calibration in Data Converters;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22

3. Design of a 10-BIT 100MSPS Sar ADC;2024 Conference of Science and Technology for Integrated Circuits (CSTIC);2024-03-17

4. A 10-bit 33.3-kS/s 3.2-fJ/conversion-step single-ended counter-type SAR ADC with dual 5-bit CDAC arrays and counters in 65-nm CMOS;AEU - International Journal of Electronics and Communications;2024-02

5. An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

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