5.2 Capacitance-to-Digital Converter for Operation Under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation-Reference-Cited by-同舟云学术

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5.2 Capacitance-to-Digital Converter for Operation Under Uncertain Harvested Voltage down to 0.3V with No Trimming, Reference and Voltage Regulation

Published:2021-02-13 Issue: Volume: Page:
ISSN:
Container-title:2021 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Aiello Orazio,Crovetti Paolo,Alioto Massimo

Funder

Ministry of Education

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9365732/9365735/09365846.pdf?arnumber=9365846

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 10-Channel, 120 nW/Channel, Reconfigurable Capacitance-to-Digital Converter for Sub-$\mu$W Robust Wearable Sensing;IEEE Transactions on Biomedical Circuits and Systems;2024-08

2. An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier;Journal of Low Power Electronics and Applications;2024-07-24

3. A 23.9-μW 13.6-Bit Period Modulation-Based Capacitance-to-Digital Converter With Dynamic Current Mirror Front-End;IEEE Solid-State Circuits Letters;2024

4. A 23.9 µW 13.6-bit Period Modulation-Based Capacitance-to-Digital Converter with Dynamic Current Mirror Front-end Achieving Capacitor Range of 1 to 68 pF;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05

5. Design of analog front-end integrated circuit of tactile sensor for human-machine interface;Integration;2023-11

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