A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time
Author:
Affiliation:
1. Analog Devices,Somerset,NJ
2. Xilinx,Cork,Ireland
3. Vishay,Cork,Ireland
4. Bosch,Valencia,Spain
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731575.pdf?arnumber=9731575
Reference5 articles.
1. 32.5 A 24GHz Self-Calibrated ADPLL-Based FMCW Synthesizer with 0.01% rms Frequency Error Under 3.2GHz Chirp Bandwidth and 320MHz/μs Slope
2. A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation
3. A rotary-traveling-wave-oscillator-based all-digital PLL with a 32-phase embedded phase-to-digital converter in 65nm CMOS
4. 26.1 A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error
5. 17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth
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1. 32.6 A 76-to-81GHz Direct-Digital 7b 14GS/s Double-Balanced I/Q Mixing-DAC Radar-Waveform Synthesizer;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
2. 10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
3. FMCW Chirp Frequency Error and Phase Noise Measurement;Synthesis Lectures on Engineering, Science, and Technology;2024
4. A 16 GHz Duty-Cycled Charge Pump PLL-Based Chirp Synthesizer;Synthesis Lectures on Engineering, Science, and Technology;2024
5. Concept Evaluation of a DDFS and RFDAC-Based FMCW Modulator;IEEE Transactions on Radar Systems;2024
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