FMCW Chirp Frequency Error and Phase Noise Measurement
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Publisher
Springer Nature Switzerland
Link
https://link.springer.com/content/pdf/10.1007/978-3-031-59773-2_4
Reference20 articles.
1. D. Cherniak, L. Grimaldi, L. Bertulessi, R. Nonis, C. Samori, S. Levantino, A 23-GHz low-phase-noise digital bang-bang PLL for fast triangular and sawtooth chirp modulation. IEEE J. Solid-State Circuits 53(12), 3565–3575 (2018). (Dec)
2. Q. Shi, K. Bunsen, N. Markulic, J. Craninckx, A self-calibrated 16-GHz subsampling-PLL-based fast-chirp FMCW modulator with 1.5-GHz bandwidth. IEEE J. Solid-State Circuits 1–10 (2019)
3. T.R. Pratap, N. Markulic, P. Wambacq, J. Craninckx, A 12-mW 10-GHz FMCW PLL based on an integrating DAC with 28-kHz RMS-frequency-error for 23-MHz/$$\mu $$s slope and 1.2-GHz chirp-bandwidth. IEEE J. Solid-State Circuits 55(12), 3294–3307 (2020)
4. Z. Shen, H. Jiang, F. Yang, Y. Wang, Z. Zhang, J. Liu, H. Liao, 32.5 A 24 GHz self-calibrated ADPLL-based FMCW synthesizer with 0.01% rms frequency error under 3.2 GHz chirp bandwidth and 320 MHz$$\mu $$s slope, in 2021 IEEE International Solid- State Circuits Conference (ISSCC), vol. 64 (2021), pp. 450–452
5. H. Shanan, D. Dalton, V. Chillara, P. Dato, A 9-to-12 GHz coupled-RTWO FMCW ADPLL with 97 fs RMS jitter, $$-120$$ dBc/Hz PN at 1 MHz offset, and with retrace time of 12.5 ns and 2 $$\mu $$s chirp settling time, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), vol. 65 (2022), pp. 146–148
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