A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks-Reference-Cited by-同舟云学术

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks

Published:2023-02-19 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Wang Bo¹,Xue Chen¹,Feng Zhongyuan¹,Zhang Zhaoyang¹,Liu Han¹,Ren Lizheng¹,Li Xiang¹,Yin Anran¹,Xiong Tianzhu¹,Xue Yeyang¹,He Shengnan¹,Kong Yuyao¹,Zhou Yongliang¹,Guo An¹,Si Xin¹,Yang Jun¹

Affiliation:

1. Southeast University,Nanjing,China

Funder

National Natural Science Foundation of China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067526.pdf?arnumber=10067526

Reference6 articles.

1. A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241 GOPS and 37.01 TOPS/W for 8b-MAC Operations for Edge-Al Devices;wu;ISSCC,2022

2. A 5-nm 254-TOPS/W 221-TOPS/mm² Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations

3. 15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications

4. A 1.041-Mb/mm² 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications

5. An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications;chih;ISSCC,2021

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