28.7 A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL-Reference-Cited by-同舟云学术

28.7 A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL

Published:2023-02-19 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Kwon Daehyun¹,Jeong Heon Su¹,Choi Jaemin¹,Kim Wijong¹,Kim Jae Woong¹,Yoon Junsub¹,Choi Jungmin¹,Lee Sanguk¹,Rie Hyunsub Norbert¹,Lee Jin-il¹,Lee Jongbum¹,Jang Taeseong¹,Kim JunHyung¹,Kang Sanghee¹,Shin Jungbum¹,Loh Yanggyoon¹,Lee Chang Yong¹,Woo Junmyung¹,Yu Hyeseung¹,Bae Changhyun¹,Oh Reum¹,Sohn Young-soo¹,Yoo Changsik¹,Lee Jooyoung¹

Affiliation:

1. Samsung Electronics,Hwaseong,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067651.pdf?arnumber=10067651

Reference6 articles.

1. 18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution

2. A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

3. 6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS

4. A 0.45-to-0.7V 1-to-6Gb/s 0.29-to-0.58pJ/b Source-Synchronous Transceiver Using Automatic Phase Calibration in 65nm CMOS;choi;ISSCC,2016

5. 25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

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