18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution-Reference-Cited by-同舟云学术

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18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution

Published:2016-01 Issue: Volume: Page:
ISSN:
Container-title:2016 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Joo Hye-Yoon,Bae Seung-Jun,Sohn Young-Soo,Kim Young-Sik,Ha Kyung-Soo,Ahn Min-Su,Kim Young-Ju,Kim Yong-Jun,Kim Young-Ju,Kim Ju-Hwan,Choi Won-Jun,Shin Chang-Ho,Kim Soo Hwan,Kim Byeong-Cheol,Ko Seung-Bum,Park Kwang-Il,Jang Seong-Jin,Jin Gyo-Young

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7405163/7417881/7418033.pdf?arnumber=7418033

Cited by 14 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

2. Research on Acceleration Technologies and Recent Advances of Data Center GPUs;2023 8th International Conference on Intelligent Computing and Signal Processing (ICSP);2023-04-21

3. 28.7 A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL;2023 IEEE International Solid-State Circuits Conference (ISSCC);2023-02-19

4. A 6-Gb/s PAM-3 Transceiver With Background Time-Varying Offset Sensing and Compensation;IEEE Solid-State Circuits Letters;2023

5. A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ;IEEE Journal of Solid-State Circuits;2023-01

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