A 4% Impedance Variation JEDEC Compatible ZQ Calibrator for DDR3, DDR4 and DDR5 SDRAM
Author:
Affiliation:
1. University of Science and Technology of China,School of Microelectronics,Hefei,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10365709/10365561/10366026.pdf?arnumber=10366026
Reference10 articles.
1. 23.2 A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme
2. 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme
3. A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface
4. A 28-Gb/s/pin PAM-4 Single-Ended Transmitter with High-Linearity and Impedance-Matched Driver and 3-Point ZQ Calibration for Memory Interfaces
5. A Heterogeneous Dual DLL and Quantization error minimized ZQ calibration for 30nm 1.2V 4Gb 3.2Gb/s/pin DDR4 SDRAM;Na;2013-VLSI
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