4.1 A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL-Reference-Cited by-同舟云学术

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4.1 A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL

Published:2023-02-19 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Solid- State Circuits Conference (ISSCC)
language:
Short-container-title:

Author:

Renukaswamy Pratap Tumkur¹,Vaesen Kristof¹,Markulic Nereo¹,Derudder Veerle¹,Park Dae-Woong¹,Wambacq Piet¹,Craninckx Jan¹

Affiliation:

1. Imc,Heverlee,Belgium

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067404.pdf?arnumber=10067404

Reference6 articles.

1. A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration

2. 17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter

3. A 9-to-12GHz Coupled-RTWO FMCW AOPLL with 97fs RMS Jitter,-120dBc/Hz PN at 1 MHz Offset, and With Retrace Time of 12. 5ns and 2µs Chirp Settling Time;shanan;ISSCC,2022

4. A 1 V 2mW 17GHz Multi-Modulus Frequency Divider Based on TSPC Louie Usina 65nm CMOS;krishna;ESSCIRC,2014

5. 17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. CMOS phase-locked loops in ISSCC 2023;Journal of Semiconductors;2023-05-01

2. A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL;IEEE Journal of Solid-State Circuits;2023

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