CMOS phase-locked loops in ISSCC 2023
Author:
Publisher
IOP Publishing
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://iopscience.iop.org/article/10.1088/1674-4926/44/5/050205/pdf
Reference7 articles.
1. A 16GHz, 41kHzrms frequency error, background-calibrated, duty-cycled FMCW charge-pump PLL;Renukaswamy;IEEE International Solid-State Circuit Conference,2023
2. A 135fsrms-jitter 0.6-to-7.7GHz LO generator using a single LC-VCO-based subsampling PLL and a ring-oscillator-based sub-integer-N frequency multiplier;Jo;IEEE International Solid-State Circuit Conference,2023
3. A 76.7fs-integrated-jitter and -71.9dBc in-band fractional-spur bang-bang digital PLL based on an inverse-constant-slope DTC and FCW subtractive dithering;Dartizio1;IEEE International Solid-State Circuit Conference,2023
4. A 32kHz-reference 2.4GHz fractional-N nonuniform oversampling PLL with gain-boosted PD and loop-gain calibration;Qiu;IEEE International Solid-State Circuit Conference,2023
5. A 9.25GHz digital PLL with fractional-spur cancellation based on a multi-DTC topology;Castoro;IEEE International Solid-State Circuit Conference,2023
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