A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration-Reference-Cited by-同舟云学术

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A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration

Published:2006-12 Issue:12 Volume:41 Page:2842-2851
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Gupta Manoj,Song Bang-Sup

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/4014593/04014614.pdf?arnumber=4014614

Cited by 47 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Fractional‐N PLL;Phase‐Locked Loops;2023-12-22

2. 4.1 A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL;2023 IEEE International Solid- State Circuits Conference (ISSCC);2023-02-19

3. A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation;IEEE Journal of Solid-State Circuits;2021-03

4. CMOS analog and mixed-signal phase-locked loops: An overview;Journal of Semiconductors;2020-11-01

5. Design of optimized high precision fractional‐N frequency synthesizer with low spur;Microwave and Optical Technology Letters;2020-03-20

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