14.1 A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving −67dBc Fractional Spur
Author:
Affiliation:
1. University of Southern California,Los Angeles,CA,United States
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067342.pdf?arnumber=10067342
Reference4 articles.
1. An Injection-Locked Ring-Oscillator-Based Fractional-N Digital PLL Supporting BLE Frequency Modulation
2. A 1.7GHz MDLL-Based Fractional-N Frequency Synthesizer with 1.4ps RMS Integrated Jitter and 3mW Power Using a 1b TOC;marucci;ISSCC,2014
3. 25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS
4. 29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. 10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
2. Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration;IEEE Journal of Solid-State Circuits;2024-01
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