10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter-Reference-Cited by-同舟云学术

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10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter

Published:2024-02-18 Issue: Volume: Page:192-194
ISSN:
Container-title:2024 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Xu Dingxin¹,Liu Zezheng¹,Kuai Yifeng¹,Huang Hongye¹,Zhang Yuncheng¹,Sun Zheng¹,Liu Bangan¹,Wang Wenqian¹,Xiong Yuang¹,Qiu Junjun¹,Madany Waleed¹,Zhang Yi¹,Fadila Ashbir Aviat¹,Shirane Atsushi¹,Okada Kenichi¹

Affiliation:

1. Tokyo Institute of Technology,Tokyo,Japan

Funder

Cadence Design Systems

Mentor Graphics

Keysight Technologies

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454284.pdf?arnumber=10454284

Reference8 articles.

1. 32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels

2. 4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

3. 14.1 A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving −67dBc Fractional Spur

4. A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS

5. 32.1 A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping ΔΣM

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